XInC wireless processor

XInC™ (pronounced "zinc") is a 16-bit pipelined RISC processor with 8 hardware threads.   The 8 threads behave as 8 independent processors, each with unrestricted access to main memory and the peripheral bus.   Additionally, the threads share hardware resources with the exception of each thread's dedicated register set.   This approach results in outstanding MIPS/gate efficiency.   The reduced efficiency of serial interrupt-based processors caused by context swapping, task scheduling, unpredictable execution times, and RTOS overheads is avoided by the XInC architecture.

Each thread is scheduled to execute at 1/8 of the system clock, thus removing the overhead of an RTOS (Real-Time Operating System).   Code is written as 8 individual programs, each running on its own thread and may be used to service one or more I/O peripherals.   In a typical wireless application 3 threads might be used to execute a wireless protocol, while the other 5 threads are made available to run other programs.   XInC is available in packaged chip, bare die, and core IP forms.